|This chapter is a collaborative effort between iNEMI and IEEEâ€™s IRDS (International Roadmap for Devices & Systems) and Heterogeneous Integration Roadmap (HIR), and the final ITRS2.0.
This chapter provides focus and direction to industry, academia and government on critical technology trends and motivations for research needed to meet next-generation semiconductor packaging requirements. Emerging packaging trends like wafer-level packaging, 2.5D and 3D integration, system in package (SiP) and heterogeneous integration are projected to be major enablers in maintaining the pace of Mooreâ€™s Law scaling. This roadmap attempts to highlight the main challenges for each of the new packaging trends, including such topics as wafer/device stacking challenges, packaging of electronic/photonic systems, and the need for coherent chip-package-system co-design, modeling and simulation. It also proposes starting point solutions to extoll the reader into developing more comprehensive and new insights towards advancing these trends or create new ones in the process of aiding packaging innovation.Â