Co-Chair: Wei Keat Loh, Intel
Co-Chair: Ron Kulterman, Flex
PresentationsEnd-of-Project Webinar presentation, September 18 & 20, 2019 (members only; requires log-in)
Impact of Low Temperature Solder on Electronic Package Dynamic Warpage Behavior and Requirements, presented by Wei Keat Loh (Intel Malaysia), ECTC 2019, May 29, 2019, Las Vegas, Nevada
Statement of Work and Project Statement
BackgroundThe iNEMI packaging workshop held in Japan in 2009 clearly identified problems with the existing warpage evaluation criteria for organic package assembly to printed circuit boards. 2013 iNEMI Roadmap described package warpage as one key challenge. Packaging technology is aggressively evolving to meet new user demands and requirements. Dynamic warpage characteristic of electronic package is critical for seamless board assembly. Hence this effort is to understand the kind of dynamic warpage demonstrated in industry. The project has accomplished 3 phases addressing metrology challenges and the recent trends of package warpage characteristics. The study and outputs of earlier phases can be found at iNEMI project webpage.
The project team has gained significant learning about different package technology dynamic warpage behavior and its comparison to existing industry standards and it gives a different perspective of how packages can react differently to temperature. The project team believes that the variety of packages considered earlier has not encompassed what is available in the market and hence the team decided to continue with the effort.
As part of the continuation from earlier phases, the scope of the project is as listed below.
More InformationContact Haley Fu