- Presentation and Recording (October 28, 2016) (iNEMI members only). You must be logged into your iNEMI member web account to view.
- This end-of-project webinar discussed the project achievements of the Warpage Characteristics of Organic Packages Project, Phase 3. The metrology used to characterize, measure, and present the dynamic warpage of electronic packages as a function of temperature has become a critical tool in the electronics industry. Existing JEDEC standard JESD22-B112A lists the four metrologies of shadow moiré, digital fringe projection, confocal and digital image correlation. Each of these has distinct advantages and disadvantages depending on the required use model and application. In Phase 3, a series of identical measurement scenarios was applied to each metrology in an attempt to establish constructive comparisons of capability and use across specific tools commonly used for each metrology today. Key parameters targeted in these evaluations included field of view (FOV), oven capabilities, measurement preparation and software capabilities. The intent is not to declare a best tool but rather to provide comparative aspects across the metrologies and tools for those considering a specific use model.
Wei Keat Loh, Intel
Ron Kulterman, Flextronics
Tim Purdie, Akrometrix
Statement of Work and Project Statement
Phase 3 Objectives
The influence of package warpage on assembly quality and reliability are receiving increasing attention across the industry. The iNEMI Warpage Characteristics of Organic Packages Project Team proposed a broad experimental program to characterize ball grid array (BGA) package warpage using ThermMoiré in Phases 1 and 2. As the project gained significant interest from industry, the project team has decided to continue with this effort. Phase 3 of the project plans to:
- Benchmark or fingerprint package warpage characteristics to develop a better understanding of the current trends of warpage behavior for different package constructions:
- Small BGA Packages
- Interposer, 2.5D, 3D stack packages, through via silicon (TSV); Memory technology (High Band Width Memory, DDR)
- Large BGA Packages
- Package stiffeners – picture frame stiffener, different stiffener attachment method, shapes and sizes
- Either organic substrate or ceramic substrate
- System In Package/Multi Chip Package (BGA)
- Stack Die or multiple die
- Die on interposer and/or with asymmetrical layout.
- Embedded Package (embedded silicon, actives and passives)
- The measurement will be done at respective tool manufacturer.
- Identify measurement methods and protocols based on the different measurement techniques and technology such as:
- Confocal techniques
- Projection moire techniques
- Thermo moire techniques with or without convective reflow
- 3D Digital Image Correlations (DIC)
- Other packaging materials and design evaluation if provided.
Presentations and Papers
Recent Trends of Package Warpage and Measurement Metrologies, presented by Wei Keat Loh (Intel) at ICEP 2016 (Sapporo, Japan; April 21, 2016)
Comparison of Advanced Package Warpage Measurement Metrologies, IEMT-EMAP 2016 (September 20-22; Penang, Malaysia)
Recent Trends of Organic Package Warpage, presented by Masahiro Tsuirya (iNEMI) at IMPACT 2015 (Taipei, Taiwan; October 22, 2015)
Recent Trends of Package Warpage Characteristic. Authors: Wei Keat Loh (Intel Technology Sdn. Bhd); Ron Kulterman (Flextronics); Tim Purdie (Akrometrix LLC); Haley Fu (iNEMI); Masahiro Tsuriya (iNEMI). Presented at iNEMI Session at ICEP 2015 (April 16, 2015; Kyoto, Japan):
Presentation, presented by Wei Keat Loh (Intel)
Paper, presented by Wei Keat Loh (Intel)
The Project Team is in the process of soliciting OCMs, OEMs, ODMs and other companies for assistance in acquiring packages for the evaluations. Eventually the output from this project could be used to develop improved warpage specifications through industry standard bodies. Click here for a list of components needed.