Advancing Manufacturing Technology

Event Calendar

Thursday, February 4, 2021

Phase 1 Report: 1st Level Interconnect Void Characterization Project - Session 2

Start Date: 2/4/2021 10:00 AM JST
End Date: 2/4/2021 11:00 AM JST


Organization Name: iNEMI

Masahiro Tsuriya
Phone: (984) 333-0820

Phase 1 Project Report: 1st Level Interconnect Void Characterization Project

Session 2
Thursday, February 4, 2021
8:00 a.m. EST (Americas)
2:00 p.m. CST (Europe)
10:00 p.m. JST (Japan)
Register for this webinar

Session 1 
Wednesday, February 3, 2021 
8:00 p.m. EST (Americas)
10:00 a.m. JST (Japan) on Thursday, February 4
Register for this webinar

The formation of small voids (micro voids) can occur in solder-based flip chip joints during the assembly process, and these voids tend to grow after multiple reflows (solid-liquid-solid). The impact of these micro voids on package performance and reliability has not been well characterized to date. For example, micro voids in 1st level interconnect materials can be a concern for applications that involve high electrical and thermal flux. Voids can also have an impact on electromigration in the joint, adversely affecting the reliability of the electrical interconnect. There are currently no guidelines or standards that define an acceptable percentage of voiding or how the percentage of voiding relates to the reliability of the assembly. Phase 1 of the 1st Level Interconnect Void Characterization project has studied voids in flip chip interconnect to determine their location and volume in an effort to understand how the voiding affects product reliability, and what level of voiding is acceptable while maintaining reliability requirements. This webinar will report Phase 1 results.