Start Date: 12/12/2019 10:00 AM JST
End Date: 12/12/2019 11:00 AM JST
Session 1 (APAC)
December 12, 2019
10:00 a.m. JST (Japan)
9:00 a.m. CST (China)
8:00 p.m. EST (USA) on Dec. 11, 2019
5:00 p.m. PST (USA) on Dec. 11, 2019
Register for Session 1
Session 2 (Americas & EMEA)
December 12, 2019
7:00 a.m. EST (USA)
1:00 p.m. CET (Europe)
9:00 p.m. JST (Japan)
8:00 p.m. CST (China)
Register for Session 2
This new iNEMI project will look at voids in 1st level interconnect, focusing on flip chip packages. Small voids (micro voids) can occur in solder-based flip chip joints during the assembly process and are a potential concern for applications that involve high electrical and thermal flux across the flip chip. They can also impact electromigration in the joint, adversely affecting the reliability of the electrical interconnect.
The small dimension of the flip chip bond and the interference of substrate and die metallization make it challenging to accurately locate and measure the size of the voids or percentage of voiding with X-ray, which is the preferred method of inspection for voids. There are currently no guidelines or standards that define an acceptable percentage of voiding or how the percentage of voiding relates to the reliability of the assembly.
The 1st Interconnect Void Characterization project plans to study voids in flip chip interconnect to determine their location and volume. It will also seek to understand how voiding in 1st level interconnect affects product reliability and what level of voiding is acceptable while maintaining reliability requirements. Click here for additional project information.
If you are interested in this project, please join us for one of our call-for-participation webinars. These webinars are open to industry (iNEMI membership is not required). Participants must register in advance — click on one of the links above to register.
For additional information, please contact Masahiro Tsuriya (firstname.lastname@example.org).