Start Date: 11/5/2020 12:00 PM EST
End Date: 11/5/2020 1:00 PM EST
iNEMI Roadmap Highlights Series: Semiconductor Technologies
Thursday, November 5
12:00 p.m. EST (Americas)
6:00 p.m. CET (EMEA)
Register for this webinar
Presenter: Paolo Gargini, PhD
The 2019 Semiconductor Technologies chapter summarizes major system characteristics in cloud computing, mobile, IoT, cyber-physical systems and quantum computing in addition to the major technology characteristics of logic and memory devices. Semiconductor design is driven by application and system requirements typically set at the beginning of any new product family design cycle and step-by-step requirements percolate through the manufacturing production chain to the semiconductor manufacturers. Electronic products, such as smart phones and other fast evolving electronics generate the requirements for new ICs and other related components. On the other hand, new devices with new capabilities diffuse upwards in the supply chain, offering system designers novel options. New lithography capabilities (i.e., EUV) after an incubation of more than 20 years finally reached manufacturing in 2018 and assure the continuation of 2D scaling for another 10 years. Since 2015 new, very creative 3D transistor, memory cell, and overall IC structures, in conjunction with 3D packaging capabilities custom developed over 25 years ago, are revolutionizing the way ICs are designed and produced. This webinar will discuss the roadmap assessment of the semiconductor industry, current challenges, risks, and novel and exciting opportunities.
Dr. Paolo Gargini has been Chairman of IEEE’s IRDS (International Roadmap for Devices & Systems) since 2016; and he chaired the ITRS (International Technology Roadmap for Semiconductors (1998-2015). Dr. Gargini worked with Intel Corporation for 34 years. He first joined to company in 1978, responsible for MPU technology. He headed Intel’s first submicron team and made flip chip packaging technology manufacturable in the mid-90s. In 1996, he became Director of Technology Strategy, Intel Fellow; and was responsible for worldwide consortia research from 1993 to 2012.
He has served on the boards of Sematech, SRC, IMEC, EIDEC and SIA, and as Chairman of the Nanoelectronics Research Initiative (NRI). He is currently a member of the Leadership Team of the International Network Generations Roadmap (INGR), an IEEE initiative. As Chairman of the I300I initiative, he led the industry-wide conversion to 300mm wafers. Dr. Gargini was inducted into the VLSI Research Hall of Fame in 2009, became an IEEE Fellow in 2009, an I-JSAP Fellow in 2014 and an IEEE Life-Fellow in 2020.
Dr. Gargini was born in Florence, Italy. He holds doctorates in Electrical Engineering and Physics. He was a researcher at Stanford University and at Fairchild Camera and Instrument in Palo Alto in the early 70s.