Advancing Manufacturing Technology

Wafer/Panel Level Package Flowability and Warpage

Initiative Leader:
Renn Chan Ooi, Intel


Call for Participation Webinar

Statement of Work and Project Statement

  • These documents are currently being developed.  If you'd like more information, contact Haley Fu.


In order to avoid the cost and quality challenges of assembling many sub-millimeter components in a package, we will rely upon wafer level packaging (WLP) as it is practiced today for electronics and future WLP approaches using reconstituted wafers and panel processing. The goal is to utilize the same parallelism in manufacturing for packaging that has driven semiconductor electronics cost reduction. Roadmap has projected wafer size increases to 450mm silicon or large panel processing varies from 370x470mm to 600x720mm.

With wafer thinning, the increasing of wafer diameter and panel size, adopting new materials and processing techniques, mold flowability becomes a concern, and warpage is becoming the primary limiting factor to support large area die and interposers. There is need for the industry to establish the range of mold material (liquid compression, granular compression, sheet lamination, etc.) with different properties to manage flowability and warpage, investigate the dispense pattern challenges (flow marks and knit lines), and understand the relationship between molding parameters, flow and tool settings with resultant warpage.

This new initiative aims to identify key processing parameters and factors that influence flowability and investigate the factors from flowability that impacts warpage. If this is a topic of your interest, please join and help us define appropriate project scope, develop the project SOW (statement of work), and establish the team/resources to enable the project.

Further Information

Haley Fu