PCB Warpage Characterization and Minimization Project
Sign up by July 15, 2017
Srinivas Aravamudhan, Intel
Call for Project Sign-Up Webinars
- Click here to fill out form to download call for participation presentation (June 14/15, 2017)
Project Statement and Statement of Work
Customer demands for smaller form factor electronic devices are driving the use of thinner electronic components and thinner printed circuit board (PCB) in the assembly process. The use of thinner components and thinner multi-up panel PCBs (≤ 40 mils) has led to PCB warpage issues in the surface mount (SMT) assembly process, which in turn impacts the PCB assembly yield. PCBs with excessive warpage impact paste print quality in print process and solder joint formation during reflow soldering leading to SMT assembly defects. Lack of industry standard for PCB warpage at reflow temperature further compounds the PCB warpage risk to SMT assembly yield.
This iNEMI project will help to explore the three vectors (PCB fabrication process, PCB design and Board assembly process conditions) and develop guidelines for each of these vectors which will help to minimize PCB warpage and improve SMT margin/yield to the benefit of participants.
Steps for Joining the Project
Please note: iNEMI membership is required to participate in this project sign-up. Sign up through July 15, 2017. We expect project participation from OEM, EMS, PCB shops, SMT equipment and tooling suppliers, warpage measurement as well as simulation service providers.
For iNEMI members:
- Complete and sign the project statement agreement
- Fax the completed statement(s) to +1 (703) 834-2735 or scan and email to email@example.com