Quantify Impact of Board Design and Process Control on SMT Performance



  • Sandeep Sane (Intel)
  • Ram Viswanath (Intel)

Upcoming Webinars

The kick-off meeting was held on July 2, 2015.  Regular meetings are set for every 2 weeks.

Next meetings (one session) are:

  • Wednesdays, 5:00 p.m. PDT (North America)
  • Thursdays, 8:00 a.m. CST (China)
  • Click here to join the meeting online.
  • The password is inemi.
  • Meeting number is 731 984 719.


  • The kick-off meeting reviewed the background that led to the proposal of this project, and discussed project scope, objectives and key variables to be considered.
  • Kick-Off Presentation (July 2, 2015)


This new initiative was proposed by iNEMI members and was selected to move forward based on our industry survey.

Warpage issues can significantly affect SMT yield.  iNEMI has ongoing projects focusing on package warpage characterization; however, the impact of board design, warpage, paste print and process temperature on SMT yield is not well understood.  This initiative proposes to study those gaps and investigate board warpage and its correlation with SMT yield. 

For more information (download PDF).

We expect active engagement from OEMs, ODMs, IC makers, materials and equipment suppliers. If this is an area of interest -- and need -- for your company, please join us in the project formation meeting. Please contact Haley Fu if you have any questions and send her the appropriate contacts at your company to be involved with this new initiative..

For Additional Information

Haley Fu