Boundary Scan Adoption Project, Phase 1

Chair:       Phil Geiger (Dell)
Co-chair:  Steve Butkovich (Cisco Systems)

End-of-Project Webinar

Congratulations to our winners!
The following three individuals received a copy of Kenneth Parker's book, “The Boundary Scan Handbook.”  Their names were drawn from the 200+ participants who responded to the iNEMI survey regarding boundary scan adoption.  

   Lakshmi Balasubramanian
   Dialogic, Inc. (Bridgewater, New Jersey, US)

   Anurag Jindal
   Freescale Semiconductor (Noida, India)

   Takashi Ugajin
   Andor System Support Co., Ltd. (Tokyo, Japan)

Thanks to everyone who participated in the survey.  We are currently analyzing the data and are scheduled to present a paper on the results at this year's International Test Conference (November 1-6 in Austin, Texas).

Project Objective
Promote wider adoption of boundary scan (IEEE 1149.1, 1149.6 and P1581) throughout the industry.  Encourage semiconductor vendors to include the technology in their products.  Promote the development of tools by ATE vendors to support boundary scan based board test.

Background
Increasing circuit densities and speeds are quickly reducing electrical test point access for printed circuit assembly test.  Boundary scan is a technology which will allow continued testability of printed circuit assemblies, but its use requires that it be designed into semiconductor devices. Currently, not all semiconductor vendors support boundary scan or do so incorrectly.  Wider availability of complying devices is necessary to enable cost efficient and effective board test for future designs.  In addition, tools to support boundary scan based test need to be developed and integrated into manufacturing test equipment.

IEEE P1581 has proposed a standard means of including test features in a memory device that can collaborate with other 1149.1 boundary scan devices without requiring boundary scan circuitry, complex controllers or dedicated test pins. The result is a memory device design suitable for printed circuit board (PCB) applications, including those where design-for-test overhead is economically unacceptable.

Design-for-test is currently not accepted in the general area of memory devices (SRAM, DRAM, flash, etc.) since 1581 is intended to dovetail in a master-slave relationship with 1149.1 (JTAG).  This project proposes to bridge the gap between board test and board manufacturing where this lack of understanding arises in the use of design-for-test.

Project Proposed Scope:

Phase 1
  • Identify potential areas of well implemented Boundary Scan – Survey Users of Devices
    • Processor
    • Memory
    • Video
    • Programmable Logic Devices
      • Gather ideas / Brainstorm
      • Share available data from participating companies
      • Identify areas of focus
  • Define Compliance
  • Develop Results/Output in White Paper
Phase 2
  • Evaluate the compliance of semiconductor devices currently in use
  • Provide Improvement and Implementation Process to Device Vendors
  • Define Methods for encouraging compliance
  • Develop Results/Output in White Paper
Phase 3
  • Develop requirements for Boundary Scan test development tools
  • Define next steps
Statement of Work (Version 3.0, May 8, 2008)

Project Statement (Version 3.0, May 8, 2008) (Sign up ends Friday, July 11, 2008)

Presentations

APEX 2008 (April 1, 2008; Las Vegas, Nevada)
   Board & Systems Manufacturing Test TIG Overview
   Boundary Scan Adoption Project

For additional information
David Godlewski
Phone: +1 717-651-0522
Email: dgodlewski@inemi.org