Wei Keat Loh, Intel
Ron Kulterman, Flextronics
Richard Coyle, Alcatel-Lucent
Statement of Work and Project Statement
This project was organized to identify primary factors that can contribute to the warpage performance of selected components during typical SMT processes. Current qualification criteria and standards are not adequate to predict good yield results at first- and second-level assemblies. Furthermore, measurement methods (dimensional and test) are neither common nor up-to-date.
This project team plans to define a qualification method and a set of criteria (e.g., sample size, precondition, variations of material and processes at the first and second levels), which would be used to evaluate warpage characteristics of new and existing packages in the design and manufacture of products. The objective is to better understand package warpage characteristics across different package types and attributes.
The proposed work would incorporate an evaluation of how to improve the package warpage qualification processes across the industry. Just like any independent body that generates independent surveys and technical assessments of existing end customer product attributes (e.g., Prismark, IEEE, IPC), the activities are to benchmark (i.e.,“fingerprint”) package warpage characteristics and identify best-in-class measurement methods / protocols. This effort will provide a piece of a large complex problem, the results of which may be used as a stepping stone for future projects.
Recent Trends of Package Warpage Characteristic. Authors: Wei Keat Loh (Intel Technology Sdn. Bhd); Ron Kulterman (Flextronics); Tim Purdie (Akrometrix LLC); Haley Fu (iNEMI); Masahiro Tsuriya (iNEMI). Presented at iNEMI Session at ICEP 2015 (April 16, 2015; Kyoto, Japan):
Presentation, presented by Wei Keat Loh (Intel)
Paper, presented by Wei Keat Loh (Intel)